1. Field of the Invention
The invention relates generally to semiconductor devices and more specifically to a semiconductor device having a gate structure or a resistor comprised of multiple layers of polysilicon where each layer of polysilicon is separated from the adjacent polysilicon layers by a thin oxide layer.
2. Description of the Prior Art
A typical field effect transistor (FET) 50 with a polysilicon gate 15 is shown in FIG. 1. The transistor 50 has a first region 10 of N+ conductivity type formed in a P conductivity type (P-type) semiconductor substrate 11. Region 10 functions as the source region of transistor 50. Laterally spaced a selected distance 14, the channel length, from source region 10 of N+ conductivity type is a second region 12 of N+ conductivity type in substrate 11. Region 12 functions as the drain of transistor 50. The region in the substrate 11 between source and drain regions 10, 12 functions as a channel region 14. A thin gate oxide layer 13 is disposed on substrate 11 so that the oxide layer 13 overlies source region 10, drain region 12, and channel region 14. Polysilicon gate 15 is formed on gate oxide layer 13. Ions of P-type conductivity impurities are implanted in the periphery of transistor 50 to form channel-stopper regions 18. A field oxide layer 17 overlies each of the regions 18. An additional oxide layer 16 overlies field oxide 17, gate oxide layer 13, and polysilicon gate 15. Finally, a drain electrode 19 and a source electrode 20 contact drain region 10 and source region 12 respectively through oxide layer 16 and gate oxide layer 13.
In a typical fabrication of transistor 50, thin gate oxide 13 is first grown on P-type substrate 11. A thick layer of silicon nitride, which functions both as an implant barrier for ion implantation and an oxidation mask, is deposited over oxide layer 13. The silicon nitride layer is removed from areas except for the areas where source region 10, drain region 12 and channel region 14 of transistor 50 are to be formed. After removal of the silicon nitride layer, P-type impurity ions are implanted to form the channel-stopper regions 18. The silicon nitride layer prevents ion implantation in the region where the source region 10, drain region 12 and channel regions 14 are to be formed. After the P-type ion implantation, substrate 11 is again oxidized to form field oxide region 17. During this operation, the silicon nitride layer functions as an oxidation mask to prevent the oxidation of the regions where the source region 10, drain region 12 and channel region 14 are to be formed.
After the oxidation step, the remaining silicon nitride layer is removed and then N-type conductivity impurity ions are implanted to form source region 10 and drain region 12. A polysilicon layer is then grown over the gate oxide layer 13. Using a mask, the polysilicon layer is etched, to form the polysilicon gate 15 and any necessary polysilicon interconnect lines (not shown). After formation of gate 15, source region 10 and drain region 12 are formed by using gate 15 as a dopant mask. Source and drain regions 10, 12 are typically formed by ion implantation. In some applications, gate 15 is doped prior to formation of source region 10 and drain region 12. After formation of source region 10 and drain region 12, oxide layer 16 is grown, and then a mask is used to form vias to source region 10 and drain region 12 respectively. Subsequently the drain and source electrodes 19 and 20 are formed by depositing a metal layer and then etching it by using one or more additional mask steps.
The use of the above-described self-aligning gate structure, i.e., the formation of source region 10 and drain region 12 using gate 15 as a mask, eliminates problems associated with metal-gate fabrication processes and consequently enhances the high frequency characteristics of transistor 50 compared with a transistor having a metal gate. However, the accuracy of location of gate 15 and source and drain regions 10, 12 formed by the self-aligning gate process depends highly upon the etching of the polysilicon layer which is in turn dependent upon the thickness of the polysilicon layer.
Typically, the polysilicon layer is etched using a plasma-etching process. Unfortunately, as illustrated in an expanded view in FIG. 2, the plasma-etching produces an upper surface 15a that is broader than a bottom surface 15b. As a result of etching of the polysilicon layer, drain and source regions 10, 12 separate from the bottom surface 15b of the polysilicon, to make transistor 50 inoperable. This is because upper surface 15a prevents impurity ions from being implanted into substrate 11 in the vicinity of the bottom surface 15b.
More specifically, if the source and drain regions 10, 12 are separated from the bottom surface 15b, the electrical path between the source and drain regions 10, 12 through channel region 14 discontinues so as to lose the transistor action. Moreover, even if transistor 50 functions, the electrical characteristic is unstable, so as to differ amongst several transistors formed simultaneously. The polysilicon layer has a poor smoothness in the upper surface and its thickness is not constant on the same substrate 11. This thickness variation results in variations in the distance between the upper and bottom surfaces 15a, 15b which cause variations in the operational characteristics of transistors formed in the same fabrication process.
One of the causes for the variations in the thickness of the polysilicon layer is the effective grain size of the polysilicon. If the grains are large, significant indentations can occur between adjacent grain boundaries. These indentations affect not only the etching but also the mask alignment because the mask must be applied over the polysilicon layer. Hence, the polysilicon gate-type FET (as in FIG. 1), while having a better frequency response than other types of insulated gate FET's, still has several disadvantages which affect both yield and electrical performance.
One attempted solution to the problems associated with the polysilicon grain size and the etching was to form the polysilicon gate in two steps. In this fabrication process, a layer equivalent to one-half the thickness of the polysilicon gate was first formed. The one-half thickness polysilicon layer was covered by a thin oxide layer and then another polysilicon layer, equivalent to one-half the thickness of the polysilicon gate, was formed on the thin oxide layer.
When the double layer of polysilicon separated by the oxide layer was etched to form the polysilicon gate, the effect of etching was less than on the single-layer polysilicon gate structure in the prior art transistor described above. Also, the upper surface of the polysilicon layer was somewhat smoother because the reduced thickness resulted in a smaller grain size. However, while the double layer polysilicon gate functions satisfactorily, the yield and performance characteristics were not significantly enhanced over the prior art transistors.